For a pipelines CPU with a single ALU, consider the following: A. The j + 1st…
2017
For a pipelines CPU with a single ALU, consider the following: A. The j + 1st instruction uses the result of jth instruction as an operand B. Conditional jump instruction C. jth and j + 1st instructions require ALU at the same time Which one of the above causes a hazard?
- A.
A and B only
- B.
B and C only
- C.
B only
- D.
A , B and C
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Correct answer: D
In a pipelined CPU with a single ALU, all three scenarios cause hazards. A represents a data hazard (Read After Write dependency). B causes a control hazard due to branch uncertainty. C creates a structural hazard because both instructions need the ALU simultaneously.
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