Control Hazards
Duration: 4 min
This video lesson is available to enrolled students.
AI Summary
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The lecture focuses on Control Hazards in pipelined processors, specifically addressing the inefficiencies caused by branch instructions. The instructor explains that when a branch instruction is encountered, the processor may have already fetched and partially executed subsequent instructions that turn out to be incorrect. This leads to a 'hazard' where these instructions must be discarded. The session transitions into a quantitative analysis, teaching students how to calculate the Cycles Per Instruction (CPI) penalty based on the frequency of branch instructions and the number of stalls they incur.
Chapters
0:00 – 2:00 00:00-02:00
The instructor begins by defining the problem of Control Hazards. He presents a scenario where instruction I1 is a branch, and the next instruction to execute is I10. However, the processor has already partially executed I1, I2, I3, which is the core problem. A flowchart is displayed, categorizing 'Branch Instruction' into 'Conditional' and 'Unconditional'. The 'Conditional' branch further splits into 'Condition true (Jump)' and 'Condition false (No Jump)'. The instructor writes a vertical sequence I1, I2, I3, I4, I5 to represent the instruction stream, emphasizing that the decision to jump is not immediate.
2:00 – 4:30 02:00-04:30
The instructor visualizes the hazard using a pipeline timing diagram with stages IF, ID, EX, and WB. He marks I1 as the branch instruction and shows red crosses over I2 and I3 in the IF and ID stages, indicating they are flushed. He then introduces a calculation problem: 'Consider a system where 20% instruction are branch instruction... Find the CPI'. He calculates the CPI for three cases. Case 1: 1 Stall results in 0.8 x 1 + 0.2 x 2 = 1.2. Case 2: 2 Stalls results in 0.8 x 1 + 0.2 x 3 = 1.4. Case 3: 3 Stalls results in 0.8 x 1 + 0.2 x 4 = 1.6. This demonstrates how stall cycles directly increase the average CPI.
The lecture effectively bridges the gap between theoretical pipeline hazards and practical performance metrics. By first illustrating the structural problem of branch instructions wasting cycles through a flowchart and timing diagram, the instructor sets the stage for the mathematical solution. The calculation of CPI serves as a practical application, showing how a 20% branch frequency with varying stall penalties (1, 2, or 3 cycles) degrades performance from a base CPI of 1.0 to 1.2, 1.4, and 1.6 respectively. This progression helps students understand the tangible cost of control dependencies in processor design.