Problem with Pipelining
Duration: 5 min
This video lesson is available to enrolled students.
AI Summary
An AI-generated summary of this video lecture.
The video is a lecture on computer architecture focusing on pipeline scheduling with variable stage delays. The instructor solves a specific problem involving 5 instructions ($I_1$ through $I_5$) where each instruction requires a different number of clock cycles for the Fetch (F), Decode (D), Execute (E), and Write Back (WB) stages. He demonstrates how to construct a pipeline diagram to determine the total execution time, accounting for stalls (X) when a stage is occupied by a previous instruction or when an instruction requires multiple cycles in a specific stage.
Chapters
0:00 – 2:00 00:00-02:00
The instructor presents a problem titled "Consider 5 instruction with following clock requirement?". A table displays instructions $I_1$ through $I_5$ with cycle counts for stages F, D, E, and WB. For instance, $I_1$ requires 1 cycle for F, 2 for D, 1 for E, and 1 for WB. Below the table is an empty grid with columns numbered 1 to 18 representing clock cycles. The instructor begins filling the grid for $I_1$, writing 'F' in column 1, 'D' in columns 2 and 3, 'E' in column 4, and 'WB' in column 5, visually demonstrating how multi-cycle stages occupy the pipeline. He underlines the values in the table as he speaks to emphasize the specific requirements.
2:00 – 5:00 02:00-05:00
The instructor proceeds to schedule the remaining instructions. For $I_2$, he places 'F' in column 2, then marks an 'X' (stall) in column 3 because the Decode stage is occupied by $I_1$. He continues with 'D' in columns 4-5, 'E' in 6-7, and 'WB' in 8. He repeats this logic for $I_3$ (requiring 2 cycles in F, 1 in D, 3 in E, 2 in WB) and $I_4$ (1 in F, 3 in D, 2 in E, 1 in WB), carefully inserting 'X' marks where stage conflicts occur. Finally, he schedules $I_5$ (1 in F, 2 in D, 1 in E, 2 in WB), completing the grid which shows the full execution timeline up to cycle 18. He writes the letters F, D, E, WB and X in red ink to distinguish the stages and stalls clearly.
5:00 – 5:28 05:00-05:28
The instructor shows a slide with text stating, "We understand that different stages in a pipeline may have different delays, it also depends on the type of instruction that how much time a particular stage will take for a specific instruction." He mentions that if each instruction takes one clock, CPI = 1. He then transitions to a new problem from "Gate 2009" involving a loop `for (I=1; I<=2; I++)` with a table of cycle requirements for 4 instructions, showing options a) 16, b) 23, c) 28, d) 30. This indicates a shift to calculating total cycles for a looped sequence.
The lecture provides a clear, step-by-step methodology for handling non-uniform pipeline stages, a common scenario in real-world processors where complex instructions take longer to execute. By manually plotting the stages, students can visualize data hazards and structural hazards that necessitate stalls. The instructor's approach emphasizes the importance of tracking resource availability (the pipeline stages) against the specific timing requirements of each instruction. This foundational skill is crucial for solving more advanced problems, such as the loop-based example introduced at the end, which requires calculating total cycles for repeated instruction sequences.