Consider a pipelined processor with the following four stages: IF: Instruction Fetch ID: Instruction Decode…

Question

Consider a pipelined processor with the following four stages:

IF: Instruction Fetch
ID: Instruction Decode and Operand Fetch
EX: Execute
WB: Write Back

The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage depends on the instruction. The ADD and SUB instructions need 1 clock cycle and the MUL instruction needs 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?

ADD       R2, R1, R0        R2 ← R1 + R0
MUL       R4, R3, R2        R4 ← R3 * R2
SUB       R6, R5, R4        R6 ← R5 - R4

Accepted Answer

Correct answer: B — The pipeline has 4 stages (IF, ID, EX, WB). ADD and SUB take 1 cycle in EX, MUL takes 3 cycles. Instruction 1 (ADD): IF(1), ID(2), EX(3), WB(4). Result R2 available after cycle 3. Instruction 2 (MUL): Depends on R2. With forwarding, EX starts at cycle 4. EX takes cycles 4-6. WB is cycle 7. Instruction 3 (SUB): Depends on R4 from MUL. EX starts at cycle 7 (after MUL EX finishes). EX takes cycle 7. WB is cycle 8. Total clock cycles = 8.

Answer

A. 7

Answer

B. 8

Answer

C. 10

Answer

D. 14

Consider a pipelined processor with the following four stages: IF: Instruction…