Data Hazards
Duration: 4 min
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The video lecture provides a comprehensive overview of Data Hazards in computer architecture, specifically within the context of pipelined processors. The instructor begins by defining data hazards as situations where instructions exhibiting data dependence modify data in different pipeline stages, which causes delays in the pipeline execution. He introduces the Bernstein condition as the underlying principle for these dependencies. The lecture categorizes hazards into three main types: RAW (Read after Write), WAR (Write after Read), and WAW (Write after Write). The session progresses from general definitions to specific, concrete examples, illustrating how these dependencies manifest in instruction sequences and cause performance issues.
Chapters
0:00 – 2:00 00:00-02:00
The instructor introduces the concept of Data Hazards using a slide titled Data Hazards. He explains that these occur when instructions with data dependence modify data in different pipeline stages, leading to delays. He lists three types: RAW (Flow/True data dependency), WAR (Anti-Data dependency), and WAW (Output data dependency). He then starts writing an example on the whiteboard to illustrate a dependency. He writes I1: a = b + c and I2: d = a + c. He circles the variable a in both instructions, drawing an arrow from the write operation in I1 to the read operation in I2. This visual aid demonstrates a Read-After-Write dependency where the second instruction needs the result of the first. He emphasizes that I2 is trying to read a before I1 has written it in the pipeline context.
2:00 – 4:18 02:00-04:18
The slide updates to provide formal definitions and examples for each hazard type. First, RAW hazard is defined: instruction J tries to read data before instruction, I write it. The example given is I: R2 <- R1 + R3 followed by J: R4 <- R2 + R3, where R2 is written by I and read by J. Next, WAR hazard is defined: instruction J tries to write data before instruction, I read it. The example is I: R2 <- R1 + R3 and J: R3 <- R4 + R5, highlighting the conflict on register R3. Finally, WAW hazard is defined: instruction J tries to write output before instruction, I write it. The example shows I: R2 <- R1 + R3 and J: R2 <- R4 + R5, both writing to R2. The instructor concludes by noting that WAR and WAW hazards typically occur during out-of-order execution. He uses red circles and arrows to visually track the read and write operations on specific registers.
The lecture systematically breaks down data hazards, starting with a high-level definition and the Bernstein condition. It then details the three specific types: RAW, WAR, and WAW. The instructor uses both handwritten examples and slide-based formal definitions to reinforce the concepts. The progression moves from a simple variable assignment example (a = b + c) to register transfer notation (R2 <- R1 + R3), making the abstract concept of pipeline hazards concrete. The distinction between hazards that occur in standard execution (RAW) versus those requiring out-of-order execution (WAR, WAW) is a key takeaway. The visual annotations, such as circling registers and drawing arrows, serve as crucial aids for understanding the flow of data and the specific points of conflict in the pipeline.