Consider a hypothetical processor with an instruction of type LW R1, 20(R2),…
20112009
Consider a hypothetical processor with an instruction of type LW R1, 20(R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of a constant 20 and the contents of register R2. Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory?
- A.
Immediate addressing
- B.
Register addressing
- C.
Register Indirect Scaled Addressing
- D.
Base Indexed Addressing
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Correct answer: D
Key idea: The instruction computes the memory address by adding a constant offset to the contents of a register and then accesses memory at that address.
Reasoning:
The effective address is formed as contents of R2 + 20, so address calculation uses a register (R2) plus a fixed displacement (20).
This is the classic base-plus-displacement (base + offset) addressing mode, often called base addressing or displacement addressing; the question labels it as base indexed addressing.
Other common addressing modes do not match: immediate addressing embeds the data in the instruction (not a memory access), register addressing uses a register as the data source, and scaled-indexed forms involve an index register multiplied by a scale factor.
Conclusion: The instruction implements base-plus-displacement addressing (described in the question as base indexed addressing).
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