Consider a 33 MHz CPU based system. What is the number of wait states required…
2014
Consider a 33 MHz CPU based system. What is the number of wait states required if it is interfaced with a 60 ns memory? Assume a maximum of 10 ns delay for additional circuitry like buffering and decoding.
- A.
0
- B.
1
- C.
2
- D.
3
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Correct answer: C
First, calculate the CPU clock period: T = 1 / f = 1 / 33 MHz ≈ 30.3 ns. Next, determine the total memory access time required: Memory Time + Circuitry Delay = 60 ns + 10 ns = 70 ns. The CPU needs enough clock cycles to cover this access time. Dividing the required time by the clock period gives 70 ns / 30.3 ns ≈ 2.31 cycles. Since the CPU cannot execute a fraction of a cycle, it must round up to 3 full clock cycles. Typically, one cycle is used for the address phase, so the remaining cycles are wait states: 3 total cycles - 1 base cycle = 2 wait states.