Practice Question
Duration: 2 min
This video lesson is available to enrolled students.
AI Summary
An AI-generated summary of this video lecture.
The video presents a worked example for calculating Effective Memory Access Time (EMAT) in a computer architecture context. The problem specifies a cache hit rate of 80%, cache access time of 5ns, and main memory access time of 100ns. The instructor calculates EMAT for both hierarchical and simultaneous access methods.
Chapters
0:00 – 2:00 00:00-02:00
The video begins with a clear problem statement displayed at the top of the screen: 'Calculate the EMAT for a machine with a cache hit rate of 80% where cache access time is 5ns and main memory access time is 100ns, both for simultaneous and hierarchical access.' The instructor systematically underlines critical values on the text, specifically 'EMAT', '80%', '5ns', and '100ns', to emphasize the variables needed for the formula. He then proceeds to write out the calculation for hierarchical access first. He writes the equation 0.8[5ns] + 0.2[5ns + 100ns], representing the hit rate multiplied by cache time plus the miss rate multiplied by the sum of cache and memory times. He calculates the first term as 4ns and the second term as 21ns, summing them to get 25ns. He draws a horizontal line to separate this from the next part and begins writing the formula for simultaneous access, starting with 0.8[5ns] + 0.2[.
2:00 – 2:16 02:00-02:16
Continuing from the previous step, the instructor completes the formula for simultaneous access. He writes the full expression 0.8[5ns] + 0.2[100ns] on the board. He performs the multiplication to get 4ns and 20ns. He adds these values together to find the final EMAT for simultaneous access, which is 24ns. He clearly underlines the final result 24ns to signify the completion of the problem. The video ends with this final answer visible on the screen alongside the previous calculation.
This lecture segment effectively contrasts two methods of calculating Effective Memory Access Time (EMAT) based on system architecture. The instructor first tackles the hierarchical access model, where a cache miss requires accessing the cache first and then the main memory, leading to a total miss penalty of 5ns + 100ns. This results in an EMAT of 25ns. He then shifts to the simultaneous access model, where the cache and main memory are accessed in parallel. In this scenario, a miss simply incurs the main memory access time of 100ns as the penalty, without the initial cache delay. This yields a slightly faster EMAT of 24ns overall.