Consider the following circuit with initial state Q0 = Q1 = 0. The D…
2001
Consider the following circuit with initial state Q0 = Q1 = 0. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.
Figure
Consider the following timing diagrams of X and C; the clock period of C <= 40 nanosecond. Which one is the correct plot of Y?
- A.
a
- B.
b
- C.
c
- D.
d
Attempted by 10 students.
Show answer & explanation
Correct answer: A
From the circuit:
D0 = X, so Q0 stores the value of X on a valid positive clock edge.
D1 = X AND Q0', and Y = Q1.
Initially Q0 = Q1 = 0. When X has been high for the required setup time before a positive edge, the old value of Q0 is still 0. Therefore, just before that edge:
D1 = X AND Q0' = 1 AND 1 = 1.
So Q1, and hence Y, becomes 1.
At the next positive clock edge, Q0 has already become 1. Therefore Q0' = 0 and:
D1 = X AND Q0' = 1 AND 0 = 0.
So Y returns to 0.
Thus Y is a single clock-period pulse corresponding to waveform (a). Hence, option A is correct.