A processor that has carry, overflow and sign flag bits as part of its program…
2008
A processor that has carry, overflow and sign flag bits as part of its program status word (PSW) performs addition of the following two 2's complement numbers 01001101 and 11101001. After the execution of this addition operation, the status of the carry, overflow and sign flags, respectively will be:
- A.
1, 1, 0
- B.
1, 0, 0
- C.
0, 1, 0
- D.
1, 0, 1
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Correct answer: B
Quick answer: Carry = 1, Overflow = 0, Sign = 0
Interpret the operands:
01001101 is +77 in two's complement.
11101001 is negative. Invert and add 1: invert -> 00010110, +1 -> 00010111 = 23, so the value is -23.
Add the values (unsigned view to find carry-out): +77 + 233 = 310 = 0x136. The low 8 bits (result byte) are 00110110 (0x36). There is a carry-out (a 9th bit) = 1.
Determine overflow for two's complement (signed) addition:
Compute carry into the most-significant bit (MSB) and carry out of the MSB: carry into MSB = 1, carry out = 1. Overflow = carry_into_MSB XOR carry_out = 1 XOR 1 = 0.
Also note: adding a positive and a negative number cannot produce signed overflow, which matches the XOR result.
Sign flag = MSB of the 8-bit result = 0 (result 00110110 is positive).
Therefore the final flags are: carry = 1, overflow = 0, sign = 0.
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