Let R1 and R2 be two 4-bit registers that store numbers in 2’s complement…

Key idea: In 4-bit two's complement the representable range is -8 to +7. Arithmetic overflow happens when the true sum lies outside this range. A quick sign check: adding two numbers with the same sign that produces a result with the opposite sign indicates overflow.

• R1 = 1011 and R2 = 1110 → 1011 = -5, 1110 = -2. Sum = -7 (1001 in 4 bits), which is within -8 to +7 → no overflow.

• R1 = 1100 and R2 = 1010 → 1100 = -4, 1010 = -6. Sum = -10, which is outside -8 to +7 → overflow. The truncated 4-bit result is 0110 (+6), showing a sign change and confirming overflow.

• R1 = 0011 and R2 = 0100 → 0011 = 3, 0100 = 4. Sum = 7, within -8 to +7 → no overflow.

• R1 = 1001 and R2 = 1111 → 1001 = -7, 1111 = -1. Sum = -8, which is within -8 to +7 → no overflow.

Conclusion: The only pair that causes arithmetic overflow is R1 = 1100 and R2 = 1010 because their true sum (-10) lies outside the representable 4-bit two's complement range.