Consider the following circuit composed of XOR gates and non-inverting…
2003
Consider the following circuit composed of XOR gates and non-inverting buffers.
The non-inverting buffers have delays d1 = 2 ns and d2 = 4 ns as shown in the figure. Both XOR gates and all wires have zero delay. Assume that all gate inputs, outputs and wires are stable at logic level 0 at time 0. If the following waveform is applied at input A, how many transition(s) (change of logic levels) occur(s) at B during the interval from 0 to 10 ns ?
- A.
1
- B.
2
- C.
3
- D.
4
Attempted by 31 students.
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Correct answer: D
The circuit consists of XOR gates and non-inverting buffers with delays d1 = 2 ns and d2 = 4 ns. The XOR gates and wires have zero delay. At time 0, all inputs are stable at logic level 0. The input A waveform transitions at specific times (e.g., 2 ns, 4 ns, etc.). The output B is affected by the XOR gate and buffer delays. Each transition in A propagates through the circuit, causing transitions at B after delay. By analyzing the timing of input changes and their propagation through the XOR gates and buffers, we find that transitions occur at B at 2 ns, 4 ns, 6 ns, and 8 ns. Thus, there are 4 transitions at B between 0 and 10 ns.
Time Interval | X(t) | X(t−4) | B(t)=X(t)⊕X(t−4) |
0 <= t < 1 | 0 | 0 | 0 |
1 <= t < 3 | 1 | 0 | 1 |
3 <= t < 5 | 0 | 0 | 0 |
5 <= t < 7 | 0 | 1 | 1 |
t >= 7 | 0 | 0 | 0 |
Conclusion
By observing the values of B(t), we can list every time it changes state:
At t = 1 ns, B transitions from
0to1.At t = 3 ns, B transitions from
1to0.At t = 5 ns, B transitions from
0to1.At t = 7 ns, B transitions from
1to0.
All 4 transitions occur well within the requested 0 to 10 ns interval.
Final Answer:
There are 4 transitions that occur at B during the interval from 0 to 10 ns.