A RAM chip has a capacity of 1024 words of 8 bits each (1K × 8). The number of…

Concept

Memory expansion uses two independent decoders. The number of memory chips fixes how many address-selection (chip-select) lines you must generate; increasing the word WIDTH adds chips in parallel but needs no extra selection lines. A 2-to-4 decoder produces 4 outputs; to obtain N selection lines you cascade these decoders in a tree: a first-level decoder produces enable signals that gate a set of second-level decoders.

Key identity: to expand a 2-to-4 decoder into a 4-to-16 decoder you take the high two address bits into ONE first-level 2-to-4 decoder, whose 4 outputs ENABLE four second-level 2-to-4 decoders driven by the low two bits.

Application to this RAM

1. Width (data bits): the RAM word is 16 bits but each chip stores 8 bits, so 16 / 8 = 2 chips are placed side by side per location. Width expansion adds chips in parallel and needs NO address decoder.

2. Depth (number of words): the RAM holds 16K words but each chip holds 1K words, so 16K / 1K = 16 banks of chips must be selected, one at a time.

3. Selecting 1 of 16 banks therefore requires a 4-to-16 decoder (because 24 = 16, four high-order address bits choose the bank).

Building the 4-to-16 decoder from 2-to-4 decoders

Arrange the 2-to-4 decoders as a two-level tree:

Result and cross-check

Total decoders = 1 (first level) + 4 (second level) = 5.

Cross-check: the first-level decoder must produce exactly 4 enables (its 4 outputs), each enabling one second-level decoder, and 4 second-level decoders × 4 outputs = 16 lines = exactly the number of banks. No decoder is spent on the width expansion. Hence 5 decoders are both necessary and sufficient.