The EX stage of a pipelined processor performs the memory read operations for…
2026
The EX stage of a pipelined processor performs the memory read operations for LOAD instructions, and the operations for the arithmetic and logic instructions. Let t𝐸𝑋 denote the time taken by the EX stage to perform the operation for an instruction. For each instruction type, the values of 𝑡𝐸𝑋 and M (the number of instructions of that type in a sequence of 100 instructions for a program P), are given in the table below.
The duration of the pipeline clock cycle is 1 nanosecond. Assume that the latch time for the interstage buffers in the pipeline is negligible.
When program P is executed, the number of clock cycles for which the pipeline is stalled due to structural hazards in the EX stage is ______. (answer in integer)
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Correct answer: 95
The pipeline clock cycle is 1 ns. The EX stage is a shared resource. If an instruction takes t_EX > 1 ns, the EX stage is occupied for multiple cycles, causing structural hazards (stalls) for subsequent instructions.
Number of cycles occupied = ceil(t_EX / 1 ns). Stall cycles per instruction = (Occupied Cycles - 1). We calculate total stalls by summing (M * Stalls) for each instruction type.
LOAD: ceil(1.8) = 2 cycles -> 1 stall * 15 = 15
IMUL: ceil(1.5) = 2 cycles -> 1 stall * 10 = 10
IDIV: ceil(2.5) = 3 cycles -> 2 stalls * 5 = 10
FADD: ceil(1.7) = 2 cycles -> 1 stall * 10 = 10
FSUB: ceil(1.7) = 2 cycles -> 1 stall * 5 = 5
FMUL: ceil(2.8) = 3 cycles -> 2 stalls * 15 = 30
FDIV: ceil(3.2) = 4 cycles -> 3 stalls * 5 = 15
Others: ceil(<1.0) = 1 cycle -> 0 stalls * 35 = 0
Total stall cycles = 15 + 10 + 10 + 10 + 5 + 30 + 15 = 95.