Delayed branching can help in the handling of control hazards The following…

GATE · 2008 · CS

Delayed branching can help in the handling of control hazards The following code is to run on a pipelined processor with one branch delay slot:

I1: ADD R2←R7+R8
I2 : SUB R4← R5-R6
I3 : ADD R1← R2+R3
I4 : STORE Memory [R4]←[R1]
BRANCH to Label if R1== 0

Which of the instructions I1, I2, I3 or I4 can legitimately occupy the delay slot without any other program modification?

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