Delayed branching can help in the handling of control hazards The following…
2008
Delayed branching can help in the handling of control hazards The following code is to run on a pipelined processor with one branch delay slot:
I1: ADD R2←R7+R8
I2 : SUB R4← R5-R6
I3 : ADD R1← R2+R3
I4 : STORE Memory [R4]←[R1]
BRANCH to Label if R1== 0Which of the instructions I1, I2, I3 or I4 can legitimately occupy the delay slot without any other program modification?
- A.
I1
- B.
I2
- C.
I3
- D.
I4
Attempted by 11 students.
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Correct answer: A
In delayed branching, the instruction in the delay slot executes regardless of whether the branch is taken. Therefore, it must be independent of the branch condition and not depend on results that may change based on the branch outcome. Here, I1 (ADD R2←R7+R8) is independent because it does not depend on the branch condition or any other instruction that may be affected by branching. I2 depends on R5 and R6, which are not involved in the branch condition but may be used later. I3 depends on R2, which is computed by I1, so it cannot be placed in the delay slot without affecting correctness. I4 depends on R1, which is computed by I3 and used in the branch condition (R1==0), so placing I4 in the delay slot would risk incorrect execution if the branch is taken. Only I1 can safely occupy the delay slot without program modification.