A pipelined processor uses a 4-stage instruction pipeline with the following…
2006
A pipelined processor uses a 4-stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). The arithmetic operations as well as the load and store operations are carried out in the EX stage. The sequence of instructions corresponding to the statement X = (S - R * (P + Q))/T is given below. The values of variables P, Q, R, S and T are available in the registers R0, R1, R2, R3 and R4 respectively, before the execution of the instruction sequence.
The number of Read-After-Write (RAW) dependencies, Write-After-Read( WAR) dependencies, and Write-After-Write (WAW) dependencies in the sequence of instructions are, respectively,
- A.
2, 2, 4
- B.
3, 2, 3
- C.
4 ,2, 2
- D.
3 ,3, 2
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Correct answer: C
The instruction sequence is: ADD R5, R0, R1; MUL R6, R2, R5; SUB R5, R3, R6; DIV R6, R5, R4. The dependencies are analyzed as follows: RAW (Read-After-Write) occurs when an instruction reads a register written by a previous instruction. WAR (Write-After-Read) occurs when an instruction writes to a register read by a previous instruction. WAW (Write-After-Write) occurs when two instructions write to the same register. For this sequence, there are 4 RAW dependencies (R5 in MUL depends on ADD; R6 in SUB depends on MUL; R5 in DIV depends on SUB; R4 is read by DIV but not written before), 2 WAR dependencies (R5 in SUB overwrites R5 from ADD; R6 in DIV overwrites R6 from MUL), and 2 WAW dependencies (R5 is written by ADD then SUB; R6 is written by MUL then DIV). The counts are 4 RAW, 2 WAR, and 2 WAW.