For a pipelined CPU with a single ALU, consider the following situations 1.…

GATE · 2003 · CS

For a pipelined CPU with a single ALU, consider the following situations 

1. The j + 1-st instruction uses the result of the j-th instruction
    as an operand
2. The execution of a conditional jump instruction
3. The j-th and j + 1-st instructions require the ALU at the same 
   time

Which of the above can cause a hazard ?

  1. A.

    1 and 2 only

  2. B.

    2 and 3 only

  3. C.

    3 only

  4. D.

    All of above

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