For a pipelined CPU with a single ALU, consider the following situations 1.…
2003
For a pipelined CPU with a single ALU, consider the following situations
1. The j + 1-st instruction uses the result of the j-th instruction
as an operand
2. The execution of a conditional jump instruction
3. The j-th and j + 1-st instructions require the ALU at the same
timeWhich of the above can cause a hazard ?
- A.
1 and 2 only
- B.
2 and 3 only
- C.
3 only
- D.
All of above
Attempted by 120 students.
Show answer & explanation
Correct answer: D
Answer: All of above.
Why each causes a hazard:
Situation 1 (j+1 uses result of j): This is a data hazard (read-after-write). The consumer instruction may need the produced value before the producer has written it back. Mitigations: forwarding/bypassing or inserting pipeline stalls until the value is available.
Situation 2 (execution of a conditional jump): This is a control hazard: the next instruction address depends on the branch outcome, so the pipeline may fetch incorrect instructions. Mitigations: branch prediction, branch delay slots, or flushing/stalling until the branch resolves.
Situation 3 (j and j+1 both require the ALU simultaneously): This is a structural hazard because a single ALU cannot service both instructions at once. Mitigations: stall one instruction, replicate the ALU/resource, or schedule instructions to avoid the conflict.
Summary: All three situations are hazards (data, control, and structural respectively). Each requires different hardware or compiler techniques to handle effectively.