An instruction pipeline has five stages, namely, instruction fetch (IF),…
2014
An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (EX), memory access (MEM), and register writeback (WB) with stage latencies 1 ns, 2.2 ns, 2 ns, 1 ns, and 0.75 ns, respectively (ns stands for nanoseconds). To gain in terms of frequency, the designers have decided to split the ID/RF stage into three stages (ID, RF1, RF2) each of latency 2.2/3 ns. Also, the EX stage is split into two stages (EX1, EX2) each of latency 1 ns. The new design has a total of eight pipeline stages. A program has 20% branch instructions which execute in the EX stage and produce the next instruction pointer at the end of the EX stage in the old design and at the end of the EX2 stage in the new design. The IF stage stalls after fetching a branch instruction until the next instruction pointer is computed. All instructions other than the branch instruction have an average CPI of one in both the designs. The execution times of this program on the old and the new design are \(P\) and \(Q\) nanoseconds, respectively. The value of \(P/Q\) is __________.
Answer: 1.54 — ConceptFor a pipeline, the clock period is the latency of its slowest stage. If a branch freezes instruction fetch until it resolves, its extra CPI…
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Correct answer: 1.54
Concept
For a pipeline, the clock period is the latency of its slowest stage. If a branch freezes instruction fetch until it resolves, its extra CPI contribution equals the branch frequency multiplied by the number of fetch-stall cycles per branch. For the same instruction count, execution time is proportional to average CPI multiplied by clock period.
Application
Old clock period: max(1, 2.2, 2, 1, 0.75) = 2.2 ns.
New clock period: max(1, 2.2/3, 2.2/3, 2.2/3, 1, 1, 1, 0.75) = 1 ns.
In the old pipeline, a fetched branch resolves at the end of the third stage, EX. Instruction fetch therefore stalls for the two intervening cycles, so the branch penalty is 2 cycles.
In the new pipeline, a fetched branch resolves at the end of the sixth stage, EX2. Instruction fetch therefore stalls for five cycles, so the branch penalty is 5 cycles.
Old average CPI = 1 + 0.20 × 2 = 1.40.
New average CPI = 1 + 0.20 × 5 = 2.00.
For the same instruction count N, P = N × 1.40 × 2.2 ns and Q = N × 2.00 × 1 ns.
Therefore P/Q = (1.40 × 2.2)/(2.00 × 1) = 3.08/2 = 1.54.
Cross-check
The new clock is 2.2 times faster, but its average CPI increases from 1.4 to 2.0, a factor of 2/1.4. Hence the old-to-new time ratio is 2.2 ÷ (2/1.4) = 1.54, confirming the calculation.
Result: P/Q = 1.54. No rounding is required because the computation terminates exactly at two decimal places.
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