Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock…
2020
Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are going to make a 5- stage pipeline out of this processor. Overheads associated with pipelining force you to operate the pipelined processor at 2 GHz. In a given program, assume that 30% are memory instructions, 60% are ALU instructions and the rest are branch instructions. 5% of the memory instructions cause stalls of 50 clock cycles each due to cache misses and 50% of the branch instructions cause stalls of 2 cycles each. Assume that there are no stalls associated with the execution of ALU instructions. For this program, the speedup achieved by the pipelined processor over the non-pipelined processor (round off to 2 decimal places) is __________ .
Attempted by 26 students.
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Correct answer: 2.15
Final answer: Speedup = 2.53 (rounded to 2 decimal places).
Non-pipelined CPI calculation:
Base cycles per instruction = 5.
Memory-stall contribution = fraction of memory instructions × miss rate × miss penalty = 0.30 × 0.05 × 50 = 0.75 cycles.
Branch-stall contribution = fraction of branch instructions × branch-miss rate × penalty = 0.10 × 0.50 × 2 = 0.10 cycles.
Total average CPI (non-pipelined) = 5 + 0.75 + 0.10 = 5.85 cycles.
Non-pipelined time per instruction:
Clock period = 1 / 2.5 GHz = 0.4 ns. Time = 5.85 × 0.4 ns = 2.34 ns per instruction.
Pipelined CPI calculation:
Ideal CPI = 1 (one instruction completed per cycle in steady state).
Memory-stall contribution = 0.30 × 0.05 × 50 = 0.75 cycles (measured in pipelined processor cycles).
Branch-stall contribution = 0.10 × 0.50 × 2 = 0.10 cycles.
Total average CPI (pipelined) = 1 + 0.75 + 0.10 = 1.85 cycles.
Pipelined time per instruction:
Clock period = 1 / 2.0 GHz = 0.5 ns. Time = 1.85 × 0.5 ns = 0.925 ns per instruction.
Speedup = (non-pipelined time) / (pipelined time) = 2.34 ns / 0.925 ns ≈ 2.5297 → 2.53.
Note: This solution assumes stall penalties (given in cycles) are counted in the clock cycles of each processor (i.e., miss/branch stall counts are measured in the respective processor's cycles).