A non pipelined single cycle processor operating at 100 MHz is converted into…
2008
A non pipelined single cycle processor operating at 100 MHz is converted into a synchronous pipelined processor with five stages requiring 2.5 nsec, 1.5 nsec, 2 nsec, 1.5 nsec and 2.5 nsec, respectively. The delay of the latches is 0.5 nsec. The speedup of the pipeline processor for a large number of instructions is
- A.
4.5
- B.
4.0
- C.
3.33
- D.
3.0
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Correct answer: C
Answer: 3.33 (approximately)
Steps:
Compute the single-cycle processor period: 1 / 100 MHz = 10 ns.
Determine the pipelined clock period: it must accommodate the slowest pipeline stage plus the latch overhead. The longest stage delay is 2.5 ns; add the latch delay 0.5 ns giving a pipeline clock period = 2.5 ns + 0.5 ns = 3.0 ns.
Calculate speedup for a large number of instructions (ignore pipeline fill/drain): speedup = single-cycle period / pipeline period = 10 ns / 3.0 ns ≈ 3.33.
Note on common mistakes: ignoring the latch delay would give 10 / 2.5 = 4.0, which is incorrect because the latch overhead must be included. A value of 3.0 confuses the pipeline period with the speedup.