We have two designs D1 and D2 for a synchronous pipeline processor. D1 has 5…
GATE · 2005 · IT
We have two designs D1 and D2 for a synchronous pipeline processor. D1 has 5 pipeline stages with execution times of 3 nsec, 2 nsec, 4 nsec, 2 nsec and 3 nsec while the design D2 has 8 pipeline stages each with 2 nsec execution time How much time can be saved using design D2 over design D1 for executing 100 instructions?
- A.
214 nsec
- B.
202 nsec
- C.
86 nsec
- D.
- 200 nsec
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