A 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and…
2025
A 5-stage instruction pipeline has stage delays of 180, 250, 150, 170, and 250, respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds. Assume that there are no pipeline stalls due to branches and other hazards. The time taken to process 1000 instructions in microseconds is __________ . (rounded off to two decimal places)
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Correct answer: 261.04
Key data: stage delays = 180 ns, 250 ns, 150 ns, 170 ns, 250 ns; inter-stage latch delay = 10 ns; pipeline depth = 5 stages.
Compute the clock cycle time: it equals the longest stage delay plus the latch delay.
Longest stage delay = 250 ns, so clock cycle time = 250 ns + 10 ns = 260 ns.
Compute the number of cycles to complete 1000 instructions: for a k-stage pipeline, total cycles = k + N - 1.
Here, k = 5 and N = 1000, so cycles = 5 + 1000 - 1 = 1004 cycles.
Total time = number of cycles × clock cycle time = 1004 × 260 ns = 261,040 ns = 261.04 µs.
Answer: 261.04 microseconds
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