Consider an instruction pipeline with four stages (S1, S2, S3 and S4) each…
2011
Consider an instruction pipeline with four stages (S1, S2, S3 and S4) each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers are as given in the figure.
What is the approximate speed up of the pipeline in steady state under ideal conditions when compared to the corresponding non-pipeline implementation?
- A.
4.0
- B.
2.5
- C.
1.1
- D.
3.0
Attempted by 178 students.
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Correct answer: B
Solution overview:
Calculate the non-pipelined execution time and the pipelined cycle time, then take their ratio.
Non-pipelined time per instruction:
Sum of all stage delays = 5 ns + 6 ns + 11 ns + 8 ns = 30 ns.
Add one pipeline register delay (output register) = 1 ns, so total = 30 ns + 1 ns = 31 ns.
Pipelined cycle time (steady state):
Clock period = maximum stage delay + pipeline register delay = 11 ns + 1 ns = 12 ns.
Speedup under ideal steady-state conditions:
Speedup = non-pipelined time / pipelined cycle time = 31 ns / 12 ns ≈ 2.583.
Approximate answer ≈ 2.6, so the closest given choice is 2.5.
Key point: pipeline throughput is limited by the slowest stage plus register overhead; total non-pipelined delay is the sum of all stages (plus any single register overhead).
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