A pipelined processor uses a 4-stage instruction pipeline with the following…
2006
A pipelined processor uses a 4-stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). The arithmetic operations as well as the load and store operations are carried out in the EX stage. The sequence of instructions corresponding to the statement X = (S - R * (P + Q))/T is given below. The values of variables P, Q, R, S and T are available in the registers R0, R1, R2, R3 and R4 respectively, before the execution of the instruction sequence.
The IF, ID and WB stages take 1 clock cycle each. The EX stage takes 1 clock cycle each for the ADD, SUB and STORE operations, and 3 clock cycles each for MUL and DIV operations. Operand forwarding from the EX stage to the ID stage is used. The number of clock cycles required to complete the sequence of instructions is
- A.
10
- B.
12
- C.
14
- D.
16
Attempted by 37 students.
Show answer & explanation
Correct answer: B
Key insight: MUL and DIV take 3 EX cycles each, ADD, SUB and STORE take 1 EX cycle, and EX->ID forwarding is available. A consumer instruction must have its ID stage coincide with the producer's last EX cycle to receive the forwarded result without extra stalls.
Instruction 1 (ADD R5, R0, R1): IF = 1, ID = 2, EX = 3, WB = 4
Instruction 2 (MUL R6, R2, R5): IF = 2, ID = 3 (receives R5 forwarded from ADD in EX cycle 3), EX = 4–6 (3 cycles), WB = 7
Instruction 3 (SUB R5, R3, R6): IF = 5, ID = 6 (receives R6 forwarded from MUL in EX cycle 6), EX = 7, WB = 8
Instruction 4 (DIV R6, R5, R4): IF = 6, ID = 7 (receives R5 forwarded from SUB in EX cycle 7), EX = 8–10 (3 cycles), WB = 11
Instruction 5 (STORE R6, X): IF = 9, ID = 10 (receives R6 forwarded from DIV in EX cycle 10), EX = 11, WB = 12
Total cycles: 12 (the final writeback completes in cycle 12).