A 5 stage pipelined CPU has the following sequence of stages: IF — Instruction…
2005
A 5 stage pipelined CPU has the following sequence of stages:
IF — Instruction fetch from instruction memory,
RD — Instruction decode and register read,
EX — Execute: ALU operation for data and address computation,
MA — Data memory access - for write access, the register read
at RD stage is used,
WB — Register write back.
Consider the following sequence of instructions:
I1 : L R0, 1oc1; R0 <= M[1oc1]
I2 : A R0, R0; R0 <= R0 + R0
I3 : S R2, R0; R2 <= R2 - R0
Let each stage take one clock cycle.What is the number of clock cycles taken to complete the above sequence of instructions starting from the fetch of I1 ?
- A.
8
- B.
10
- C.
12
- D.
15
Attempted by 65 students.
Show answer & explanation
Correct answer: A
Answer: 8 cycles.
Reasoning: Baseline pipeline cost for three instructions = number of stages + instructions - 1 = 5 + 3 - 1 = 7 cycles. A load followed immediately by an instruction that uses the loaded register causes a one-cycle load-use hazard stall. The ALU result from the second instruction can be forwarded to the third, so no additional stall is required. Therefore total = 7 + 1 = 8 cycles.
Cycle 1: I1 - IF
Cycle 2: I1 - RD, I2 - IF
Cycle 3: I1 - EX, I2 - RD, I3 - IF
Cycle 4: I1 - MA, I2 - (stall/bubble), I3 - RD
Cycle 5: I1 - WB, I2 - EX (uses forwarded load data), I3 - (stall/bubble)
Cycle 6: I2 - MA, I3 - EX (uses forwarded ALU result from I2)
Cycle 7: I2 - WB, I3 - MA
Cycle 8: I3 - WB
Summary: One load-use stall inserted between the first and second instruction is sufficient; total completion time = 8 cycles.