Consider a system that has a cache memory unit and a memory management unit…
2026
Consider a system that has a cache memory unit and a memory management unit (MMU). The address input to the cache memory is a physical address. The MMU has a translation lookaside buffer (TLB). Assume that when a page is evicted from the main memory, the corresponding blocks in the cache are marked as invalid.
For a given memory reference, which of the following sequences of events can NEVER happen?
- A.
TLB miss, Page table hit, Cache hit
- B.
TLB hit, Page table miss, Cache hit
- C.
TLB miss, Page table miss, Cache hit
- D.
TLB miss, Page table miss, Cache miss
Attempted by 29 students.
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Correct answer: B, C
A TLB hit implies the page table entry is valid and present in memory. A Page Table Miss indicates the virtual address is unmapped, triggering a page fault. Without a valid physical translation from the MMU, the cache cannot be accessed successfully because it requires a physical address. Therefore, a Cache Hit is impossible during a Page Table Miss. Additionally, a valid TLB entry contradicts the condition of a Page Table Miss as they cannot both be true for the same address translation. Thus, sequences combining these events are logically impossible.