In a \(k\)-way set associative cache, the cache is divided into \(v\) sets,…

GATE · 2013 · CS · Computer Science & IT

In a kk-way set associative cache, the cache is divided into vv sets, each of which consists of kk lines. The lines of a set are placed in sequence one after another. The lines in set ss are sequenced before the lines in set (s+1)(s+1). The main memory blocks are numbered 0 onwards. The main memory block numbered jj must be mapped to any one of the cache lines from

  1. A.

    (j mod v)∗k to (j mod v)∗k+(k−1)(j \ mod \ v) * k \ to \ (j \ mod \ v) * k + (k-1)

  2. B.

    (j mod v) to (j mod v)+(k−1)(j \ mod \ v) \ to \ (j \ mod \ v) + (k-1)

  3. C.

    (j mod k) to (j mod k)+(v−1)(j \ mod \ k) \ to \ (j \ mod \ k) + (v-1)

  4. D.

    (j mod k)∗v to (j mod k)∗v+(v−1)(j \ mod \ k) * v \ to \ (j \ mod \ k) * v + (v-1)

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