If the associativity of a processor cache is doubled while keeping the…
2014
If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected?
- A.
Width of tag comparator
- B.
Width of set index decoder
- C.
Width of way selection multiplexor
- D.
Width of processor to main memory data bus
Attempted by 289 students.
Show answer & explanation
Correct answer: D
Answer: Width of processor to main memory data bus is not affected.
Reasoning:
Cache capacity relates to number of sets, associativity, and block size by: C = S × E × B, where S = number of sets, E = associativity (ways), and B = block size.
If capacity (C) and block size (B) are unchanged and associativity (E) is doubled, the number of sets (S) must halve to keep the equality. That changes the set index bit count (log2(S)).
Because the set index bit count changes, the tag field size (address bits minus set index minus block offset) also changes. The tag comparator width depends on tag size, so it can be affected.
Doubling associativity increases the number of ways. The way-selection multiplexer must select among more ways (more inputs or more select bits), so its implementation width or control width will change.
The processor-to-main-memory data bus width is an external system parameter unrelated to the internal organization of the cache. Changing associativity (with capacity and block size fixed) does not alter this bus width.
Therefore, the only quantity listed that is guaranteed to be NOT affected by doubling associativity under the given constraints is the processor-to-main-memory data bus width.