A CPU has a cache with block size 64 bytes. The main memory has k banks, each…
2006
A CPU has a cache with block size 64 bytes. The main memory has k banks, each bank being c bytes wide. Consecutive c − byte chunks are mapped on consecutive banks with wrap-around. All the k banks can be accessed in parallel, but two accesses to the same bank must be serialized. A cache block access may involve multiple iterations of parallel bank accesses depending on the amount of data obtained by accessing all the k banks in parallel. Each iteration requires decoding the bank numbers to be accessed in parallel and this takes. k/2 ns The latency of one bank access is 80 ns. If c = 2 and k = 24, the latency of retrieving a cache block starting at address zero from main memory is:
- A.
92 ns
- B.
104 ns
- C.
172 ns
- D.
184 ns
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Correct answer: D
Solution: compute iterations and per-iteration latency.
Bytes retrieved per iteration = number of banks × bank width = 24 × 2 = 48 bytes.
Number of iterations = ceil(block size / bytes per iteration) = ceil(64 / 48) = 2 iterations.
Decoding time per iteration = k/2 = 24/2 = 12 ns.
Bank access latency per iteration = 80 ns.
Total latency = iterations × (decoding time + bank access latency) = 2 × (12 + 80) = 184 ns.
Answer: 184 ns