In a two-level cache system, the access times of \(L_1\) and \(L_2\) caches…

In a two-level cache system, the access times of  $L_1$ and $L_2$ caches are 1 and 8 clock cycles, respectively. The miss penalty from the $L_2$ cache to main memory is 18 clock cycles. The miss rate of $L_1$ cache is twice that of$​​L_2$. The average memory access time (AMAT) of this cache system is 2 cycles. The miss rates of $L_1$ and $​​L_2$ respectively are