A certain processor deploys a single-level cache. The cache block size is 8…
2019
A certain processor deploys a single-level cache. The cache block size is 8 words and the word size is 4 bytes. The memory system uses a 60-MHz clock. To service a cache miss, the memory controller first takes 1 cycle to accept the starting address of the block, it then takes 3 cycles to fetch all the eight words of the block, and finally transmits the words of the requested block at the rate of 1 word per cycle. The maximum bandwidth for the memory system when the program running on the processor issues a series of read operations is __________× 10^6 bytes/sec.
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Correct answer: 160
Key data: word size = 4 bytes; block = 8 words → block size = 32 bytes; clock = 60 MHz.
Cycle breakdown:
1 cycle to accept the starting address.
3 cycles to fetch the entire block internally.
8 cycles to transmit the 8 words at 1 word per cycle.
Total cycles per block = 1 + 3 + 8 = 12 cycles. Cycle time = 1/60,000,000 s, so time per block = 12/60,000,000 s = 200 × 10^-9 s.
Bandwidth calculation: 32 bytes / 200 × 10^-9 s = 160 × 10^6 bytes/sec.
Final answer: 160 × 10^6 bytes/sec