Consider a system with a processor and a 4 KB direct mapped cache with block…
GATE · 2026 · CS · Set 2 · Computer Science & IT
Consider a system with a processor and a 4 KB direct mapped cache with block size of 16 bytes. The system has a 16 MB physical memory. Four words P, Q, R, and S are accessed by the processor in the same order 10 times. That is, there are a total of 40 memory references in the sequence P, Q, R, S, P, Q, R, S,…
Assume that the cache memory is initially empty. The physical addresses of the words are given below (1 word =1 byte).
P: 0x845B32, Q: 0x845B26, R: 0x845B36, S: 0x846B32
Which of the following statements is/are true
Note: 1K=210 and 1M=220
- A.
Every access to P results in a cache miss
- B.
Every access to R results in a cache hit
- C.
Every access to Q results in a cache miss
- D.
Except the first access to S, all subsequent accesses to S result in cache hits
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