Consider the logic circuit given below. The inverter, AND and
2014
Consider the logic circuit given below.
The inverter, AND and OR gates have delays of 6, 10 and 11 nanoseconds respectively. Assuming that wire delays are negligible, what is the duration of glitch for Q before it becomes stable?
- A.
5
- B.
11
- C.
16
- D.
17
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Correct answer: A
To determine the glitch duration, we analyze the propagation delays along the two paths from input A to the XOR gate inputs.
1. Top Path: Input A goes through an Inverter (6 ns) and then into the AND gate (10 ns). Total delay = 6 + 10 = 16 ns.
2. Bottom Path: Input A goes directly into the OR gate (11 ns). Total delay = 11 ns.
A glitch occurs at the XOR gate inputs due to the difference in arrival times. The duration of this glitch is the absolute difference between the two path delays: 16 ns - 11 ns = 5 ns.