A 4-stage pipeline has the stage delays as 150, 120, 160 and 140 nanoseconds…
2004
A 4-stage pipeline has the stage delays as 150, 120, 160 and 140 nanoseconds respectively. Registers that are used between the stages have a delay of 5 nanoseconds each. Assuming constant clocking rate, the total time taken to process 1000 data items on this pipeline will be
Answer: C. 165.5 microseconds — Key insight: the clock period must accommodate the slowest stage plus the register delay. Find the maximum stage delay: max(150, 120, 160, 140) = 160 ns. Add…
- A.
120.4 microseconds
- B.
160.5 microseconds
- C.
165.5 microseconds
- D.
590.0 microseconds
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Correct answer: C
Key insight: the clock period must accommodate the slowest stage plus the register delay.
Find the maximum stage delay: max(150, 120, 160, 140) = 160 ns.
Add the register delay to get the clock period: 160 ns + 5 ns = 165 ns per cycle.
Compute the number of clock cycles to process 1000 items in a 4-stage pipeline: cycles = stages + items - 1 = 4 + 1000 - 1 = 1003 cycles.
Total time = 1003 cycles × 165 ns = 165,495 ns = 165.495 microseconds ≈ 165.5 microseconds.
Final answer: 165.495 microseconds (approximately 165.5 microseconds).
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