Consider a 5-stage pipelined processor with Instruction Fetch (IF),…
2024
Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT?
Answer: A. In a pipelined execution, forwarding means the result from a source stage of an earlier instruction is passed on to the destination stage of a later instruction; C. Forwarding cannot prevent all pipeline stalls — ConceptForwarding, or bypassing, is a hardware technique that sends an in-flight result directly from a pipeline register to a later instruction that needs…
- A.
In a pipelined execution, forwarding means the result from a source stage of an earlier instruction is passed on to the destination stage of a later instruction
- B.
In forwarding, data from the output of the MEM stage can be passed on to the input of the EX stage of the next instruction
- C.
Forwarding cannot prevent all pipeline stalls
- D.
Forwarding does not require any extra hardware to retrieve the data from the pipeline stages
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Show answer & explanation
Correct answer: A, C
Concept
Forwarding, or bypassing, is a hardware technique that sends an in-flight result directly from a pipeline register to a later instruction that needs it, without waiting for an ordinary register-file read after writeback. A valid forwarding path must also satisfy cycle timing: the producer value must exist before the consumer stage samples its input. Forwarding removes many RAW delays, but it does not remove every pipeline stall.
Application
The statement defining forwarding as a result passed from an earlier instruction to the consuming stage of a later instruction expresses the bypassing principle.
For the learner’s example, let the older load be I0: R0 ← MEM[LOC−1] and the immediately dependent instruction be I1: R1 ← 2 × R0. In cycle t, I0 is in MEM while I1 would be in EX. The load value appears only at the end of cycle t, but I1 needs R0 at the beginning of that cycle, so a bubble is required. In cycle t+1, I1 can receive the held value from the MEM/WB pipeline register by forwarding; this saves waiting for a later register-file read after WB. Read literally without the implicit stall-free, back-to-back convention, the phrase “can be passed” can describe this post-bubble forwarding path. The official GATE final key nevertheless excludes the MEM-output-to-next-EX statement, so the exam’s intended axis is the direct stage-to-stage transfer during the original overlap of immediately successive instructions.
The statement that forwarding cannot prevent all stalls accounts for the load-use bubble as well as control and structural hazards, none of which is eliminated merely by adding bypass paths.
The statement denying extra hardware conflicts with the implementation of forwarding, which requires bypass wires, multiplexers, destination-register comparators, and selection control.
Cross-check
Cycle t−1: I0 is in EX and I1 is in ID; the address for the load is computed, but the loaded value does not yet exist.
Cycle t: I0 is in MEM and I1 would be in EX; memory produces R0 only at the end of the cycle, which is too late for I1’s EX input at the beginning of the same cycle, so I1 must stall.
Cycle t+1: the loaded value is held in MEM/WB and I1 enters EX; a bypass can now supply R0 to I1. Forwarding reduces the delay, but the one-cycle load-use bubble remains.
Result
Under the official GATE interpretation, the accepted statements are the definition of forwarding and the statement that forwarding cannot prevent all pipeline stalls. The broader post-bubble reading of the MEM-output wording is technically understandable, but it is not the reading used by the final key. The no-extra-hardware statement is also not accepted.
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