Consider three floating point numbers A, B and C stored in registers RA, RB…

Concept: IEEE-754 single-precision format

A 32-bit IEEE-754 single-precision pattern packs 1 sign bit (bit 31), an 8-bit biased exponent (bits 30–23, bias 127), and a 23-bit mantissa (bits 22–0). The decoded magnitude is 1.fraction (binary) multiplied by 2 raised to (stored exponent − 127); the sign bit fixes the overall sign.

Application: decode each register

1. RA = 0xC1400000 → binary 1100 0001 0100 0000 0000 0000 0000 0000: sign = 1 (negative), exponent field = 100000102 = 130, unbiased exponent = 130 − 127 = 3, mantissa fraction = .1000000… → 1.5. So A = −(1.5 × 23) = −12.

2. RB = 0x42100000 → sign = 0 (positive), exponent field = 100001002 = 132, unbiased exponent = 132 − 127 = 5, mantissa fraction = .0010000… → 1.125. So B = +(1.125 × 25) = 36.

3. RC = 0x41400000 → sign = 0 (positive), exponent field = 100000102 = 130, unbiased exponent = 130 − 127 = 3, mantissa fraction = .1000000… → 1.5. So C = +(1.5 × 23) = 12.

With A = −12, B = 36, C = 12, evaluate each statement:

1. A + C = −12 + 12 = 0 — this equality holds.

2. C = A + B checks 12 against −12 + 36 = 24; since 12 ≠ 24, this equality fails.

3. B = 3C checks 36 against 3 × 12 = 36; the equality holds.

4. (B − C) > 0 checks 36 − 12 = 24 > 0; the inequality holds.

Cross-check

Three of the four statements verify directly from the decoded magnitudes (A + C, B versus 3C, and B − C), leaving exactly one statement whose two sides disagree — confirming a single, unambiguous false statement rather than the multiple mismatches a mis-decoded register would produce.

Hence the statement “C = A + B” is the one that is FALSE.