A computer system has an L1 cache, an L2 cache, and a main memory unit…
2010
A computer system has an L1 cache, an L2 cache, and a main memory unit connected as shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16 words. The memory access times are 2 nanoseconds. 20 nanoseconds and 200 nanoseconds for L1 cache, L2 cache and main memory unit respectively.
When there is a miss in both L1 cache and L2 cache, first a block is transferred from main memory to L2 cache, and then a block is transferred from L2 cache to L1 cache. What is the total time taken for these transfers?
Answer: C. 902 nanoseconds — Key insight: transfers happen in 4-word bus beats. The 16-word block from main memory arrives at L2 in four 4-word transfers, and L2 then supplies one 4-word…
- A.
222 nanoseconds
- B.
888 nanoseconds
- C.
902 nanoseconds
- D.
968 nanoseconds
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Correct answer: C
Key insight: transfers happen in 4-word bus beats. The 16-word block from main memory arrives at L2 in four 4-word transfers, and L2 then supplies one 4-word transfer to L1.
Main memory → L2: 16-word block, bus width 4 words ⇒ 4 transfers. Each transfer incurs main-memory access (200 ns) plus L2 access (20 ns) = 220 ns per transfer. Total = 4 × 220 ns = 880 ns.
L2 → L1: L1 block size is 4 words, so L2 sends one 4-word transfer. That transfer costs L2 access (20 ns) plus L1 access (2 ns) = 22 ns.
Total time for both transfers = 880 ns + 22 ns = 902 ns.
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