In an SR latch made by cross coupling two NAND gates, if both S and R inputs…
2007
In an SR latch made by cross coupling two NAND gates, if both S and R inputs are set to 0, then it will result in
- A.
Q=0, Q' = 1
- B.
Q=1, Q' = 0
- C.
Q=1, Q' = 1
- D.
Indeterminate states
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Correct answer: C
Concept: In a cross-coupled NAND SR latch, each NAND gate's output feeds into the other gate as an input, alongside its own control line (S or R). A NAND gate's output is 1 whenever ANY of its inputs is 0, and drops to 0 only when ALL its inputs are 1 - so driving a control line to 0 forces that gate's output to 1 immediately, overriding whatever the feedback loop was doing before.
Applying this to S = 0, R = 0:
Gate 1 (which outputs Q) receives S and the feedback Q' from Gate 2. With S = 0 present, Gate 1's NAND output is forced to 1 no matter what Q' currently is, so Q = 1.
Gate 2 (which outputs Q') receives R and the feedback Q from Gate 1. With R = 0 present, Gate 2's NAND output is also forced to 1 no matter what Q currently is, so Q' = 1.
Both gates resolve independently and simultaneously to 1, so the latch settles at Q = 1, Q' = 1.
Cross-check: A valid SR latch must keep Q and Q' complementary (exactly one high) so the feedback loop can 'remember' a value; Q = Q' = 1 breaks that, which is why S = R = 0 is the forbidden input combination. This is not the same as the latch's indeterminate/race condition - that only arises later, if S and R are BOTH released from 0 back to 1 at the exact same instant; simply holding S = R = 0 resolves deterministically to Q = 1, Q' = 1 as shown above.