Consider the circuit shown below. Which of the following is true?
Consider the circuit shown below. Which of the following is true?

Answer: C. f = x1 x2 + x1’x2’ — A 2:1 multiplexer implements one fixed identity: Y = S0′I0 + S0I1 — it passes I0 through when the select line S0 = 0, and I1 through when S0 = 1. When several…
- A.
f = x1’+ x2
- B.
f = x1’x2 + x1x2′
- C.
f = x1 x2 + x1’x2’
- D.
none
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Correct answer: C
A 2:1 multiplexer implements one fixed identity: Y = S0′I0 + S0I1 — it passes I0 through when the select line S0 = 0, and I1 through when S0 = 1. When several 2:1 MUXes are cascaded, this SAME identity is applied stage by stage, plugging in each stage’s actual I0, I1 and S0 — which may be a constant, a primary variable, or an earlier stage’s output — never a fresh formula for the whole chain.
Stage 1 (leftmost MUX): I0 = 1, I1 = 0, select S0 = x1. So Y1 = x1’·1 + x1·0 = x1’ — exactly the value already marked on the wire feeding the next stage.
Stage 2 (middle MUX): I0 = Y1 = x1’, I1 = x1 (tapped from the same select line driving stage 1), select S0 = x2. So Y2 = x2’·x1’ + x2·x1 = x1’x2’ + x1x2.
Stage 3 (rightmost MUX): I0 = Y2, I1 = x2 (tapped from stage 2’s select line), select S0 = x1. So f = x1’·Y2 + x1·x2 = x1’(x1’x2’ + x1x2) + x1x2 = x1’x2’ + 0 + x1x2 = x1x2 + x1’x2’.
Cross-check with two input pairs confirms the cascade: at x1 = 0, x2 = 0, stage 1 gives Y1 = 1, stage 2 gives Y2 = 1, stage 3 gives f = 1 — matching x1x2 + x1’x2’ = 1 at (0, 0). At x1 = 1, x2 = 0, stage 1 gives Y1 = 0, stage 2 gives Y2 = 0, stage 3 gives f = 0 — again matching the same expression evaluated at (1, 0). So f is 1 exactly when x1 and x2 agree (the XNOR relation), which is precisely f = x1x2 + x1’x2’, not its complement (the XOR form) and not ‘none’, since a definite expression does exist.