Which of the following memory is used to minimize memory–processor speed…

2022

Which of the following memory is used to minimize memory–processor speed mismatch?

Answer: D. Cache memoryThe CPU executes instructions far faster than main memory (RAM) can supply data or instructions to it; this gap is the processor–memory speed mismatch. Cache…

  1. A.

    UVEPROM

  2. B.

    Flash memory

  3. C.

    DVD

  4. D.

    Cache memory

Attempted by 3423 students.

Show answer & explanation

Correct answer: D

The CPU executes instructions far faster than main memory (RAM) can supply data or instructions to it; this gap is the processor–memory speed mismatch. Cache memory is a small, high-speed memory (typically SRAM) placed between the CPU and main memory specifically to bridge this gap: it holds copies of the instructions and data the CPU is most likely to need again, exploiting temporal and spatial locality of reference.

Applying this to the question: when the CPU issues a memory request, the cache is checked first. On a cache hit, the data returns at near-processor speed instead of waiting for a full main-memory access cycle, which lowers the Average Memory Access Time (AMAT). This is exactly the speed-matching role the question is asking about, and only one option performs it:

  • UVEPROM (Ultra-Violet Erasable PROM) is a non-volatile ROM variant used to hold firmware/BIOS code; it sits outside the fast CPU–memory access path and does nothing to narrow the speed gap.

  • Flash memory is non-volatile secondary storage (used in SSDs and USB drives); it is itself much slower than RAM, so it cannot compensate for CPU speed.

  • DVD is an optical secondary-storage medium for bulk data, orders of magnitude slower than main memory, and is not part of the processor's working-memory path at all.

Cross-checking against the standard memory hierarchy (registers → cache → main memory → secondary storage such as flash/DVD), cache memory is the only layer positioned immediately below the CPU registers to smooth the register-to-RAM speed transition — confirming cache memory as the answer.

Explore the full course: Bpsc

Loading lesson…