A pipelined processor uses a 4-stage instruction pipeline with the following stages: Instruction fetch (IF),…

ASHI DUBEY

A pipelined processor uses a 4-stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). The arithmetic operations as well as the load and store operations are carried out in the EX stage. The sequence of instructions corresponding to the statement X = (S - R * (P + Q))/T is given below. The values of variables P, Q, R, S and T are available in the registers R0, R1, R2, R3 and R4 respectively, before the execution of the instruction sequence.
ADD R5, R0, R1
MUL R6, R2, R5

  • SUB R5, R3, R6

  • DIV R6, R5, R4

  • STORE R6, X

The IF, ID and WB stages take 1 clock cycle each. The EX stage takes 1 clock cycle each for the ADD, SUB and STORE operations, and 3 clock cycles each for MUL and DIV operations. Operand forwarding from the EX stage to the ID stage is used. The number of clock cycles required to complete the sequence of instructions is

So, I came across the above PYQ, and my doubt is, since it is mentioned in the above question that "Operand forwarding from the EX stage to the ID stage is used", shouldn't ID stage of the current instruction be the one to receive the operands from the previous instruction's EX stage in case of data dependency. Although normally we pass the operands from EX to EX but since, it is mentioned here, shouldn't it be passed to the ID stage? making the answer = 15 clocks. Solution below. Please correct me if i have misinterpreted the sentence!
Inst | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |

---------------------------------------------------------------------------------

I1 | IF | ID | E | W | | | | | | | | | | | |

I2 | | IF | X | ID | E | E | E | W | | | | | | | |

I3 | | | | IF | X| X | X | ID | E | W | | | | | |

I4 | | | | | | | | IF | X | ID | E | E | E | W | |

I5 | | | | | | | | | | IF | ID | X | X | E | W |

Comments

  • KG AI MentorKG AI Mentor

    Quick Answeroperand forwarding from EX to ID is actually a typo in the question; standard forwarding goes from EX to EX (or pipeline register input) for data hazards. Key StepsOperand forwarding typically bypasses the ID stage, sending results directly to EX input for faster resolution. The solution table correctly assumes forwarding from previous EX stage output to next instruction's EX stage input (or ID-to-EX pipeline register). Forwarding from EX to ID would require holding data through the entire ID stage, defeating the purpose of early forwarding. — KG AI Mentor 🤖

  • Arpan Banerjee

    @ashidubey Dear Learner, I have attached the correct pipeline diagram for this question's solution. Please have a look.

    • ASHI DUBEY

      @kg_mentor_arpan_banerjee But this is exactly like EX->EX operand forwarding approach, (i.e. EX->EX fwding would give the same answer) then how is EX->ID different from EX->EX. I thought since, its EX->ID the ID would have to wait 1 stall to get the output of the previous instructions Execute stage (e.g in your diagram I2's ID would happen in clock 4 rather than 3) otherwise how will EX forward the operand to ID (as they are both in the same cycle).?

    • Arpan Banerjee

      @ashidubey The diagram is correct if it assumes an EX→ID forwarding path with combinational (same-cycle) bypassing. this question is very old so here some concept are assumption based otherwise your approach is correct. Here's why: • In Cycle C3: - ADD is in the EX stage and computes its result. - MUL is in the ID stage waiting for that operand. • The ALU result is generated during the EX stage and, before the clock edge, is directly forwarded through a combinational bypass network to the ID stage. • The ID stage does not read the old register file value. Instead, the forwarding logic (MUX/comparator) selects the forwarded ALU output, and this value is latched into the ID/EX pipeline register at the end of Cycle C3. Therefore, both instructions can occupy EX and ID in the same cycle without an explicit stall. This is different from EX→EX forwarding only in the destination of the forwarded data: - EX→EX: Forwarded to the ALU inputs of the next instruction's EX stage. - EX→ID: Forwarded to the operand-selection logic in the ID stage. We assumes that the combinational delay (ALU delay + forwarding wire delay + MUX delay + setup time) fits within one clock period. Hence, no extra stall is shown. In contrast, if the processor follows the conventional synchronous pipeline model (where EX completes only at the clock edge), EX→ID forwarding cannot occur in the same cycle, and one additional stall would be required. So, the image is not wrong—it is based on a pipeline model that assumes same-cycle combinational EX→ID forwarding rather than the more common synchronous pipeline timing.