We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3…

The "Repeated State" Problem: The sequence is: 0→1→0→2→0→3.

• The output 0 (binary 00) occurs 3 times in the cycle.

• However, each '0' must go to a different next number (1, 2, or 3).

• This means the counter needs to "remember" which of the three '0's it is currently at.

Distinguishing the Zeros:

• Since the output bits (Q1​Q0​) are fixed at 00 for all three zeros, we cannot use them to differentiate the states.

• We need extra bits (MSBs) to act as a "tag" to distinguish these three occurrences.

• To distinguish 3 items, we need ⌈log2​3⌉=2 additional bits.

Total Calculation:

2 bits (for output value)+2 bits (internal state tags)=4 Flip-Flops

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