The state diagram of a finite state machine (FSM) designed to detect an…
GATE · 2017 · EC · Set 2 · Electronics and Communication Engineering
The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input ‘In’ and an output ‘Out’. The initial state of the FSM is S0.
If the input sequence is 10101101001101, starting with the left-most bit, then the number of times ‘Out’ will be 1 is ________.
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