In the latch circuit shown, the NAND gates have non-zero, but unequal…

GATE · 2017 · EC · Set 1 · Electronics and Communication Engineering

In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input condition is: P = Q = ‘0’. If the input condition is changed simultaneously to P = Q = ‘1’, the outputs X and Y are

1. A.

   X = ‘1’, Y = ‘1’

2. B.

   either X = ‘1’, Y = ‘0’ or X = ‘0’, Y = ‘1’

3. C.

   either X = ‘1’, Y = ‘1’ or X = ‘0’, Y = ‘0’

4. D.

   X = ‘0’, Y = ‘0’

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