Consider the following multiplexer where I0,I1,I2,I3 are four data input lines…
GATE · 2002 · CS · Question 2 subpartsModified — slightly modified from the official paper; see the solution
Consider the following multiplexer where I0,I1,I2,I3 are four data input lines selected by two address line combinations A1A0=00,01,10,11 respectively and f is the output of the multiplexer. EN is the enable input.
The function f(x,y,z) implemented by the above circuit is:
- A.
xyz′
- B.
xy+z
- C.
x+y
- D.
None of these
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