Multilevel Paging

Duration: 8 min

This video lesson is available to enrolled students.

Return to /learn/SSC-JE-IMD-SCIENTIFIC-ASSISTANT-COMPUTER-SCIENCE/operating-system/memory-management/multilevel-paging/asset-multilevel-paging after enrolling

Inside: a video lesson and guided study material.

Module outline

  1. General Intelligence & Reasoning: Analogy, Non Verbal Reasoning (Spatial Aptitude) (Spatial Reasoning) (Visual Reasoning), Series (Number and Letter Series) (Numerical Relations and Reasoning), Coding Decoding, Blood Relations, Directions (Direction Test), Ranking, Order and Sequence, Logical Sequence Of Words, Syllogisms, Venn Diagram, Deductive and Inductive Reasoning (Logical Deduction and Induction) (Prepositional Reasoning), Selection Decision Table (Decision Making), Data Sufficiency, Puzzle Solving (Puzzles), Data Arrangement, Cubes & Dices, Calendar, Clock, Arithmetic, Number System, HCF LCM, Verbal Analogy (Word Based Analogy), Visual Recognition and Figure Completion, Paper Folding and Cutting, Transformation of Shapes, Clocks and Calendars, Direction Sense, Cubes and Dice, Patterns in Two-Dimensional Figures, Seating Arrangements, Analogy and Classification, Logical Deduction and Induction, Alphabet and Word Tests, Mathematical Operations, Series Completion, Simplification and Approximation, Coding and Decoding, Numerical Reasoning, Assembling and Grouping of Shapes, Three-Dimensional Patterns and Visualization, Vocabulary, Number System, Averages, Mixtures and Alligation, Simple and Compound Interest, Percentages, Algebra, Speed, Time and Distance, Seating and Arrangement Puzzles, Traverse Surveying, Order, Ranking and Sequence, Constraint Puzzles, Syllogisms and Venn Diagrams, Reading Comprehension, Critical Reasoning, Permutations and Combinations, Narrative Sequencing, Project Monitoring, Resources and Safety, Profit, Loss and Discount, Ratio and Proportion, Time and Work, Mensuration, Data Interpretation, Powers, Surds and Logarithms, Sequences and Series, Articles and Determiners, Sentence Completion, Data Sufficiency, Blood Relations, Simple Interest and Compound Interest, Mixture and Alligation, Sequence and Series (Series), Speed Time and Distance, Algebra, Profit and Loss, Powers and Exponents (Surds and Indices), Permutation and Combination
  2. General Awareness: Physics, Chemistry, Biology, History, Geography, Polity, Indian Economy, Environment, Static General Knowledge, GK- Current Affairs, Artificial Intelligence, MS Office Applications, Terms & Abbreviations, Keyboard Shortcuts, Evolution of Indian Banking (Banking & Financial Awareness), Emerging Tech Trends
  3. Engineering Mathematics: Set Theory, Relations, Functions, Graph Theory, Group Theory, Propositional and Predicate Logic, Linear Algebra, Calculus, Probability, Statistics, Signal Space and Optimum Detection, Probability, Statistics
  4. Digital Logic: Digital Systems & Boolean Basics, Logic Gates & Hardware, Boolean Expression, Boolean Minimization, Combinational Circuit, Sequential Circuits, Number System, Number Representation, Floating Point Rep, Number Systems and Codes, Registers and Counters, Boolean Algebra and Logic Gates, Microprocessors and Microcontrollers, Logic Families and CMOS Logic, Microprocessors, Logic Gates and Boolean Algebra, Minimization of Boolean Functions, Timing, Hazards and Testing, Logic Families, Combinational Logic Design, Arithmetic Circuits, Waveform Generators and Timer Circuits, Semiconductor Memories and Programmable Logic Devices, Combinational Logic Circuits, Latches and Flip-Flops, Finite State Machines, Sequential Circuits and State Machines, Minimization of Boolean Functions, Arithmetic Circuits, Latches and Flip-Flops, Number Systems and Codes, Registers and Counters
  5. Computer Organisation & Architecture: Basics of COA, Cache Memory Organization, Input Output Organisation, Pipelining, Instr Formats & Modes, Control Unit Design, Programming the Basic Computer, Register Transfer and Microoperations, Semiconductor Memories and Programmable Logic, Processor Organization and Instructions, Memory Hierarchy and Input/Output, Registers and Counters
  6. Programming & Data Structures: C Fundamentals, Control Flow, Functions, Arrays & Pointers, Storage Classes, Structures & Enums, DMA, Macros, Scoping & File Handling, Introduction to DS, Array, Stack, Queue, Linked List, Tree, Graphs, Hashing, HTML Basics, OOPS with C++, Java, Object Oriented Technology
  7. Databases: Basics of DBMS, ER Diagram, Relational Model & Functional Dependencies, Keys & Integrity Constraints, Normalization (1NF - BCNF), Decomposition Properties & 4NF, File Organization & Indexing, Relational Algebra, SQL, Relational Calculus, Transaction Management, Concurrency Control, Database Recovery, Database Security & Authorization
  8. Algorithms: Algorithm Analysis, Time Complexity Analysis, Sorting Algorithms, Greedy Algorithms, Dynamic Programming, Minimum Spanning Trees, Shortest Path Algos
  9. Theory of Computation: Introduction to TOC, Deterministic FA (DFA), Non-Deterministic FA, Regular Expressions, Grammar, Regular Language Properties, Moore & Mealy Machines, Pushdown Automata & CFG, Turing Machines, Complexity Theory
  10. Compiler Design: Intro to Compilers, Lexical Analysis, Grammar & CFG, Syntax Analysis: Top-Down, Syntax Analysis: Bottom-Up, Semantic Analysis & SDT, Intermediate Code Gen, Code Optimization, Run Time Environment
  11. Operating System: Introduction to OS, Process Management, CPU Scheduling, Process Synchronization, Threads & Process Creation, Deadlock, Memory Management, Virtual Memory, Disc Scheduling, File Management, Security, Windows OS, Distributed Systems, Unix OS, Linux OS
  12. Computer Networks: Introduction to CN, DLL: Access Control, DLL: Flow Control, DLL: Error Control, DLL: Framing, Data Link Layer - Ethernet, Net Layer: IPv4 & Proto, Net Layer: IP Addressing, Net Layer:Routing Protocol, Transport Layer Services, TL: Congestion & UDP, Application Layer, Hardware Basics, Data Communication, Website, Browser & Services, Web Design & Development, Network Security, Cyber Threats and Malware Attacks, Cyber Safety and Security
  13. Full Length Mock Tests:
  14. Sectional Tests:
  15. Paper 2 - Full-length Mock Tests:
AI summary & chapters

AI Summary

An AI-generated summary of this video lecture.

The lecture addresses the memory management challenge posed by modern systems supporting large logical address spaces ranging from 2^32 to 2^64 bits. The instructor begins by illustrating the problem: a single page table for such a system could contain millions of entries, making it impossible to fit into a single memory frame. He introduces the solution known as Multilevel Paging or Hierarchical Paging. This method involves dividing the page table into smaller pieces, effectively paging the page table itself. The specific implementation discussed is a two-level paging algorithm. A 32-bit logical address is segmented into three distinct parts: the first 10 bits serve as an index for the outer page table, the next 10 bits index the inner page table, and the final 12 bits act as the offset within the physical page frame. This hierarchical approach ensures that only the necessary portions of the page table reside in memory at any given time.

Chapters

  1. 0:00 – 2:00 00:00-02:00

    The instructor starts the session by drawing a tall vertical rectangle on the whiteboard and labeling it 5m to represent a page table with 5 million entries. He explains that in modern systems, the logical address space is so large that the page table becomes excessively big. He draws a second, smaller rectangle next to the first one to visually contrast the sizes. He then begins sketching a system diagram on the left side of the board, drawing a box labeled CPU and connecting it to memory structures. This visual setup prepares the ground for explaining why a single large page table is problematic for memory allocation. He emphasizes that the page table itself takes up a lot of space in memory.

  2. 2:00 – 5:00 02:00-05:00

    He continues the whiteboard diagram by adding a PTBR Page Table Base Register box that points to a structure labeled Outer Page Table. He draws a second structure below it labeled Inner Page Table and uses arrows to show the data flow from the CPU through these tables to the main memory. He writes V3 < 4 P > I on the board, likely referring to virtual page number logic or a specific addressing scheme. He explains that the page table itself is paged, meaning it is divided into smaller pieces that can be loaded into memory frames as needed. This avoids the requirement for a contiguous block of memory for the entire page table, solving the space issue. He draws squiggly lines to represent the memory frames being filled.

  3. 5:00 – 7:36 05:00-07:36

    The video transitions to a slide titled Multilevel Paging Hierarchical Paging. The text on the slide explicitly states that page tables can contain millions of entries and cannot be accommodated into a single frame. The diagram on the slide shows a 32-bit logical address divided into 10 bits, 10 bits, and 12 bits. The instructor points to the Outer Page Table and Inner Page Table columns, explaining how the first 10 bits index the outer table, the next 10 bits index the inner table, and the final 12 bits provide the offset within the physical page. He traces the path from the CPU through the page tables to the physical memory, reinforcing the concept of hierarchical lookup. The slide also shows the physical address being split into 32 bits for the frame number and 12 bits for the offset.

The lesson progresses from identifying the memory inefficiency of large page tables to implementing a hierarchical solution. By breaking the page table into multiple levels, the system only needs to load the necessary parts of the page table into memory, saving significant space. The 32-bit address example concretely demonstrates how bits are allocated to navigate this hierarchy. This approach allows operating systems to manage very large address spaces efficiently without wasting memory on unused page table entries. The instructor effectively uses both hand-drawn diagrams and a structured slide to clarify the complex mapping process involved in multilevel paging.

Loading lesson…