Efficiency of Stop and Wait Protocol - ARQ
Duration: 6 min
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Module outline
- General Intelligence & Reasoning: Analogy, Non Verbal Reasoning (Spatial Aptitude) (Spatial Reasoning) (Visual Reasoning), Series (Number and Letter Series) (Numerical Relations and Reasoning), Coding Decoding, Blood Relations, Directions (Direction Test), Ranking, Order and Sequence, Logical Sequence Of Words, Syllogisms, Venn Diagram, Deductive and Inductive Reasoning (Logical Deduction and Induction) (Prepositional Reasoning), Selection Decision Table (Decision Making), Data Sufficiency, Puzzle Solving (Puzzles), Data Arrangement, Cubes & Dices, Calendar, Clock, Arithmetic, Number System, HCF LCM, Verbal Analogy (Word Based Analogy), Visual Recognition and Figure Completion, Paper Folding and Cutting, Transformation of Shapes, Clocks and Calendars, Direction Sense, Cubes and Dice, Patterns in Two-Dimensional Figures, Seating Arrangements, Analogy and Classification, Logical Deduction and Induction, Alphabet and Word Tests, Mathematical Operations, Series Completion, Simplification and Approximation, Coding and Decoding, Numerical Reasoning, Assembling and Grouping of Shapes, Three-Dimensional Patterns and Visualization, Vocabulary, Number System, Averages, Mixtures and Alligation, Simple and Compound Interest, Percentages, Algebra, Speed, Time and Distance, Seating and Arrangement Puzzles, Traverse Surveying, Order, Ranking and Sequence, Constraint Puzzles, Syllogisms and Venn Diagrams, Reading Comprehension, Critical Reasoning, Permutations and Combinations, Narrative Sequencing, Project Monitoring, Resources and Safety, Profit, Loss and Discount, Ratio and Proportion, Time and Work, Mensuration, Data Interpretation, Powers, Surds and Logarithms, Sequences and Series, Articles and Determiners, Sentence Completion, Data Sufficiency, Blood Relations, Simple Interest and Compound Interest, Mixture and Alligation, Sequence and Series (Series), Speed Time and Distance, Algebra, Profit and Loss, Powers and Exponents (Surds and Indices), Permutation and Combination
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- Digital Logic: Digital Systems & Boolean Basics, Logic Gates & Hardware, Boolean Expression, Boolean Minimization, Combinational Circuit, Sequential Circuits, Number System, Number Representation, Floating Point Rep, Number Systems and Codes, Registers and Counters, Boolean Algebra and Logic Gates, Microprocessors and Microcontrollers, Logic Families and CMOS Logic, Microprocessors, Logic Gates and Boolean Algebra, Minimization of Boolean Functions, Timing, Hazards and Testing, Logic Families, Combinational Logic Design, Arithmetic Circuits, Waveform Generators and Timer Circuits, Semiconductor Memories and Programmable Logic Devices, Combinational Logic Circuits, Latches and Flip-Flops, Finite State Machines, Sequential Circuits and State Machines, Minimization of Boolean Functions, Arithmetic Circuits, Latches and Flip-Flops, Number Systems and Codes, Registers and Counters
- Computer Organisation & Architecture: Basics of COA, Cache Memory Organization, Input Output Organisation, Pipelining, Instr Formats & Modes, Control Unit Design, Programming the Basic Computer, Register Transfer and Microoperations, Semiconductor Memories and Programmable Logic, Processor Organization and Instructions, Memory Hierarchy and Input/Output, Registers and Counters
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- Algorithms: Algorithm Analysis, Time Complexity Analysis, Sorting Algorithms, Greedy Algorithms, Dynamic Programming, Minimum Spanning Trees, Shortest Path Algos
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- Computer Networks: Introduction to CN, DLL: Access Control, DLL: Flow Control, DLL: Error Control, DLL: Framing, Data Link Layer - Ethernet, Net Layer: IPv4 & Proto, Net Layer: IP Addressing, Net Layer:Routing Protocol, Transport Layer Services, TL: Congestion & UDP, Application Layer, Hardware Basics, Data Communication, Website, Browser & Services, Web Design & Development, Network Security, Cyber Threats and Malware Attacks, Cyber Safety and Security
- Full Length Mock Tests:
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AI summary & chapters
AI Summary
An AI-generated summary of this video lecture.
This lecture explains the efficiency of the Stop and Wait ARQ protocol, deriving the formula η = 1 / (1 + 2a) and calculating effective bandwidth. The instructor begins by defining efficiency as the ratio of useful transmission time (Tt) to total cycle time, which includes waiting periods for acknowledgments. Through algebraic simplification, the formula is reduced to a function of 'a', representing the ratio of propagation delay (Tp) to transmission time. The session concludes with a numerical example calculating throughput based on efficiency and bandwidth.
Chapters
0:00 – 2:00 00:00-02:00
The instructor introduces the concept of efficiency for Stop and Wait ARQ, displaying a slide titled "Efficiency(n):" with the initial formula Useful Time / Total Cycle time = Tt / (Tt + 2 * Tp). He explains that useful transmission time is Tt, while the remaining 2 * Tp represents waiting time for processing. The derivation proceeds by dividing both numerator and denominator by Tt, resulting in the simplified expression n = 1 / (1 + 2 * Tp/Tt). The variable 'a' is defined as the ratio Tp / Tt, leading to the final efficiency formula η = 1 / (1 + 2a).
2:00 – 5:00 02:00-05:00
The lecture continues with the derivation of the efficiency formula η = 1 / (1 + 2a), emphasizing that total time consists of transmission and propagation delays while queuing and processing delays are negligible. A handwritten note on the slide identifies 2 * Tp as Round Trip Time (RTT). The instructor then transitions to defining Throughput or Effective Bandwidth using the formula: Throughput = η * B. This section solidifies the relationship between efficiency and actual data transfer rates, preparing for a numerical application.
5:00 – 5:43 05:00-05:43
The instructor calculates the effective bandwidth for a Stop and Wait protocol by substituting values into the formula Throughput = η * B. With an efficiency (η) of 0.5 and bandwidth (B) of 10 Mbps, the calculation yields a final throughput of 5 Mbps. The result is written and underlined on screen as "5 x 10 Mbps = 5 Mbps". The instructor then begins to illustrate the concept with a diagram representing data frames, visualizing how efficiency impacts frame transmission.
The lecture systematically derives the efficiency metric for Stop and Wait ARQ, starting from fundamental time components. The core formula η = 1 / (1 + 2a) highlights how propagation delay relative to transmission time degrades performance. By defining 'a' as Tp/Tt, the instructor simplifies complex timing relationships into a single variable. The final application demonstrates that even with high bandwidth, low efficiency significantly reduces effective throughput, as shown in the 5 Mbps result from a 10 Mbps link. This progression from theoretical derivation to practical calculation reinforces the importance of minimizing propagation delay in network design.

