Which logic gate is used to detect overflow in 2's complement arithmetic? ISRO…

In 2's complement arithmetic, overflow occurs when the carry into the sign bit differs from the carry out of the most significant bit. This condition is mathematically represented as V = C_in XOR C_out, which requires an XOR operation to evaluate the difference between these two carries. Consequently, standard digital logic design utilizes an XOR gate connected to these carry signals to detect overflow conditions accurately.