The below figure shows four $\text{D}$-type flip-flops connected as a shift…

The below figure shows four $\text{D}$-type flip-flops connected as a shift register using a $\text{XOR}$ gate. The initial state and three subsequent states for three clock pulses are also given.

$$\begin{array}{|l|c|c|c|c|}\hline\text{State}&Q_A&Q_B&Q_C&Q_D\\\hline\text{Initial}&1&1&1&1\\\text{After the first clock}&0&1&1&1\\\text{After the second clock}&0&0&1&1\\\text{After the third clock}&0&0&0&1\\\hline\end{array}$$

The state $Q_AQ_BQ_CQ_D$ after the fourth clock pulse is