Set Associative Mapping Part-2

Duration: 4 min

This video lesson is available to enrolled students.

Return to /learn/DSSSB-TGT-COMPUTER-SCIENCE-COMPLETE-COURSE/computer-systems-architecture/cache-memory-organization/set-associative-mapping/asset-set-associative-mapping-part-2 after enrolling

Inside: a video lesson and guided study material.

Module outline

  1. About Course: About the Course
  2. Section A: General Awareness: Polity, Physics, Biology, Chemistry, Static General Knowledge, History, Geography, Indian Economy, GK- Current Affairs, Evolution of Indian Banking (Banking & Financial Awareness), Environment
  3. Section A: General Intelligence & Reasoning ability: Series (Number and Letter Series) (Numerical Relations and Reasoning), Coding Decoding, Data Sufficiency, Non Verbal Reasoning (Spatial Aptitude) (Spatial Reasoning) (Visual Reasoning), Analytical Reasoning (Counting Figures Reasoning), Blood Relations, Syllogisms, Deductive and Inductive Reasoning (Logical Deduction and Induction) (Prepositional Reasoning), Seating Arrangements, Directions (Direction Test), Puzzle Solving (Puzzles), Calendar, Clock, Cubes & Dices, Selection Decision Table (Decision Making), Logical Sequence Of Words, Crypt Arithmetic, Venn Diagram, Data Arrangement, Inequality, Analogy, Ranking, Order and Sequence, TCS NQT Advanced Reasoning Ability
  4. Section A: Arithmetical & Numerical Ability: Ratio and Proportion (Ratios), Divisibility Rules, Data Interpretation, Mixture and Alligation, Permutation and Combination, Logarithm, Number System, HCF LCM, Sequence and Series (Series), Speed Time and Distance, Percentage, Average, Profit and Loss, Simple Interest and Compound Interest, Time and Work, Pipe and Cistern, Mensuration and Geometry, Powers and Exponents (Surds and Indices), Algebra, Probability, Mental Ability, Age Problems, Partnership, Statistics, Arithmetic, Speed Mathematics and Basic Mathematics, Miscellaneous
  5. Section A: English Language & Comprehension: Vocabulary, Subject Verb Agreement (Verb Noun Agreement), Adjectives, Tenses, Comprehension / Reading Comprehension / Unseen Passages (Critical Reasoning) (Paragraph Questions), Articles, Sentence Construction, Preposition, Direct and Indirect Speech, Sentence Completion (Fill in the blanks), Sentence Re-arrangements (Para Jumbles) (Narrative Sequencing), Modals, Active Passive Voice (Voice), Sentence Correction (Error Correction), Adverb, Conjunction, Cloze Test (Cloze Passage)
  6. Section A: Hindi Language & Comprehension: भाषा, लिपि, ध्वनि, वर्ण, अक्षर, स्वर, व्यंजन, मात्रा और संयुक्ताक्षर, वर्तनी, वर्ण-विन्यास, अनुस्वार, अनुनासिक, चंद्रबिंदु और ‘र’ के रूप, शब्द, पद और शब्द-भेद, संज्ञा और सर्वनाम, विशेषण और क्रिया, लिंग, वचन, पुरुष और कारक, काल, वाच्य, वाक्य और वाक्य-भेद, संधि, समास, विलोम शब्द, पर्यायवाची शब्द, सामान्य अशुद्धियाँ, अनेक शब्दों के लिए एक शब्द, मुहावरे और लोकोक्तियाँ, अपठित गद्यांश और अपठित पद्यांश, Multi-Topic Content (Cross-Concept Material), वर्णमाला
  7. Section B: Programming, Data Structures, OOP & Java: C Fundamentals, Control Flow, Functions, Arrays & Pointers, Storage Classes, Structures & Enums, DMA, Macros, Scoping & File Handling, Introduction to DS, Array, Stack, Queue, Linked List, Tree, Graphs, Hashing, Java, OOPS with C++, Language Design, Intro to Compilers, Visual Basics, Syntax Analysis: Bottom-Up, Object Oriented Technology
  8. Section B: Computer Networks, TCP/IP & Network Security: Introduction to CN, Data Communication, DLL: Flow Control, DLL: Access Control, DLL: Error Control, Data Link Layer - Ethernet, Net Layer: IPv4 & Proto, Net Layer: IP Addressing, Transport Layer Services, TL: Congestion & UDP, Application Layer, Hardware basics, Network Access Technologies, Network Security, Society, Law & Ethics, Mobile Computing, Net Layer:Routing Protocol, Cyber Safety and Security
  9. Section B: Teaching Methodology: Child Development, Concept of Pedagogy, Theories, Inclusive Education, Experiential Pedagogy, Assessment & Evaluation, Curriculum Framework & Reforms, National Education Policy (NEP) 2020, Psychology, Teaching-Learning Process, Personality Development, Teaching Methods & Strategies, Learning and Motivation, Learners & Learning Process, Factors Affecting Teaching, Methods of Teaching, Nature, Objectives & Characteristics of Teaching, Teaching-Learning Aids & ICT Integration, Classroom Management & Communication, Evaluation, Assessment & Measurement, Curriculum & School Environment, Inclusive Education & Special Needs, Professional Development & Ethics
  10. Section B: Digital Electronics / Boolean Logic: Digital Systems & Boolean Basics, Logic Gates & Hardware, Boolean Expression, Boolean Minimization, Combinational Circuit, Sequential Circuits, Number System, Number Representation, Analog-Digital Conversion
  11. Section B: Operating Systems & Linux: Introduction to OS, Process Management, CPU Scheduling, Process Synchronization, Threads & Process Creation, Deadlock, Memory Management, Virtual Memory, File Management, Disc Scheduling, Unix OS, Linux OS, Distributed Systems, Windows OS
  12. Section B: Data Base Management System: Basics of DBMS, ER Diagram, Relational Model & Functional Dependencies, Keys & Integrity Constraints, Normalization (1NF - BCNF), Decomposition Properties & 4NF, Relational Algebra, SQL, File Organization & Indexing, Transaction Management, Concurrency Control, Database Security & Authorization, Database Recovery, Data Warehousing & Mining
  13. Section B: Internet & Web Technologies: Website, Browser & Services, Internet Fundamentals, Web Design & Development, Protocols & Services, Web Publishing & Hosting, Server Side & Security, HTML Basics, CSS, Emerging Technologies, JavaScript-Basics, .Net Programming, Electronic Data Interchange and E-Commerce, XML
  14. Section B: Computer Fundamentals, IT Basics & Architecture: Basics of COA, Cache Memory Organization, Input Output Organisation, Register Transfer and Microoperations, Control Unit Design, Programming the Basic Computer, Terms & Abbreviations, MS Office Applications, Instr Formats & Modes, Floating Point Rep
  15. Section B: Python Language: Introduction to Python, Tokens, Variables, Data Types, I/O, Operators & Expressions, Control Flow & Looping, Collections & Strings, Functions & Modules, File Handling & Data Analysis
  16. Section B: Software Engineering: Fundamentals of Software Engineering, Software Requirements and Quality Assurance, Software Design, Estimation and Metrics, Software Testing, Software Maintenance and Configuration Management, extras, Fundamentals of Systems and Information Systems
  17. Section B: Design & Analysis of Algorithms: Algorithm Analysis, Time Complexity Analysis, Sorting Algorithms, Greedy Algorithms, Dynamic Programming, Minimum Spanning Trees, Shortest Path Algos, Advanced Algorithms
  18. Section B: Mathematics: Linear Algebra, Calculus, Trigonometry, Vectors, Set Theory, Functions, Relations, Propositional and Predicate Logic, Research Process Steps, Graph Theory
  19. Section B: Computer Graphics, Multimedia & Mobile Computing: Basics of Computer Graphics, 2-D Geometrical Transforms and Viewing, 3-D Object Representation, Geometric Transformations and Viewing, Multimedia
  20. Section B: Emerging Trends: Emerging Tech Trends, Knowledge Representation, Natural Language Processing
  21. DSSSB Previous Year Paper:
  22. Business Studies and Management: Business Communication, Business Organization and Management, Financial Accounting, Business Economics, Management Information System (MIS), Knowledge Management & New Economy
AI summary & chapters

AI Summary

An AI-generated summary of this video lecture.

The video lecture focuses on set-associative cache mapping in computer architecture. The instructor begins by defining the structure of physical addresses and cache lines, specifically breaking down the address into Tag, Set, and Block Offset fields. He uses diagrams to illustrate how main memory blocks are mapped to cache sets. The lecture progresses to a concrete example involving a 2-way set-associative cache with 4 cache lines (2 sets) and 16 main memory blocks. Finally, the hardware implementation of this mapping is explained using a block diagram showing multiplexers, comparators, and the selection logic.

Chapters

  1. 0:00 – 2:00 00:00-02:00

    The instructor introduces the formula for the number of sets and breaks down the physical address structure. He displays a diagram where the 'Main Memory (Physical Address)' is split into 'Block Number' and 'Block Offset'. He annotates the diagram with bit counts, writing '8' for the Block Number and '2' for the Block Offset. He then transitions to the cache structure, showing 'Tag', 'Set', and 'Block Offset'. He writes '2' for Tag bits and '2' for Cache Line (Set) bits in one example, and later '3' for Tag and '1' for Set in another, illustrating how address bits are allocated. He writes 'Bits Transferred' with values like '2w', '4w', '3w', '8w', likely referring to word sizes or data transfer widths associated with the cache lines. He circles 'Set 1' in the lower diagram to emphasize the set selection process.

  2. 2:00 – 4:17 02:00-04:17

    The lecture moves to a specific mapping example. A diagram shows a cache with 'Set Number-0' (containing CL-0, CL-1) and 'Set Number-1' (containing CL-2, CL-3) connected to main memory blocks B-0 through B-15. The instructor writes a binary address '1001 01' at the top. He draws lines connecting specific cache lines to memory blocks, highlighting B-8 and B-9. A detailed table is shown mapping Set Numbers to Cache Lines (CL-0 to CL-3) and listing the specific Blocks (B-0, B-2, etc.) and Words (W-0, W-1, etc.) stored in each. The instructor then presents a 'Hardware Architecture' diagram for 2-Way Set Associative Mapping. This diagram illustrates the flow from Tag, Set Number, and Block Offset inputs through Multiplexers to select a set, then through Comparators to check the Tag, and finally through an OR gate to produce the result. He highlights 'Set-1 (Selected)' in the cache memory block to demonstrate the selection mechanism.

The video provides a comprehensive overview of set-associative cache mapping, starting from theoretical address breakdown to practical hardware implementation. The instructor effectively uses diagrams to visualize the relationship between main memory blocks and cache sets, demonstrating how address bits are partitioned into Tag, Set, and Offset. The transition from abstract formulas to a concrete 2-way set-associative example with 16 memory blocks helps clarify the mapping process. The final hardware architecture diagram ties the concepts together by showing the physical components like multiplexers and comparators required to execute the mapping logic, ensuring students understand both the logical structure and the physical realization of cache memory systems.

Loading lesson…